Replace the inline serial stubs (which just instantly set TX-complete)
with a proper sub-device implementation supporting:

- I/O interface mode (mode 0): Synchronous clocked serial using SCLK
  pin. Supports both internal (baud rate generator) and external
  (IOC=1) clock sources. TX double buffering with auto-load from
  buffer to shift register. Pre-outputs bit 0 on TXD before first
  clock edge so receiver can sample it on the rising edge.

- Baud rate generator: Configurable via BRxCR register with divisor
  and clock source selection. Timer drives SCLK at the configured
  rate. Clock frequency derived from CPU clock.

- TX/RX data callbacks: txd(), rxd(), sclk_out(), sclk_in() for
  connecting external devices to the serial ports.

- tx_start callback: Signals the start of each byte transmission with
  the current PFFC pin function state, allowing connected devices to
  distinguish real transmissions from phantom ones.

The serial registers (SC0BUF/SC1BUF, SC0CR/SC1CR, SC0MOD/SC1MOD,
BR0CR/BR1CR) are now delegated to the sub-devices in the internal
memory map. TX-complete flags (INTES0/INTES1 bit 7) are set at
device_reset to indicate empty TX buffers at power-on.

UART modes (7/8/9-bit) are recognized but not yet implemented.

Also moves interrupt register indices from a file-scope enum to
public static constexpr members of tmp94c241_device.